The present invention relates generally to a semiconductor memory device having a self-testing capability, and, more particularly, pertains to a semiconductor memory device having a self-testing capability based on the BIST (Built-In Self-Test) technology and a self-redundancy capability.
Before a plurality of semiconductor chips formed on a wafer are separated by dicing, the semiconductor chips in a wafer state are subjected to an operational test by using an external testing device. As the recent semiconductor memory devices have faster operation speeds and larger capacities, a test chip called BOST (Built-Off-chip Self-Test), or BIST (Built-In Self-Test) which is a self-testing circuit formed in advance in each chip is used in an operational test in order to assist such an external testing device.
A semiconductor memory device equipped with not only a self-testing circuit but also a self-redundancy circuit has also been proposed. When a memory block which contains a defective cell is detected in an operational test, the self-redundancy circuit switches access from the memory block to a redundant memory block.
Semiconductor memory devices which have a BIST-based self-testing capability and a self-redundancy capability are disclosed in the following publications.
Japanese Laid-Open Patent Publication No. 11-238393 discloses a memory device which stores the address of a defective cell, when detected in the BIST-based operational test, into a register mounted on a chip. In the normal operation of the memory device, when access is made to a defective cell, the access to the defective cell is switched to a redundant cell based on the address stored in the register.
Japanese Laid-Open Patent Publication Nos. 3-116497, 2000-311497 and 9-311824 and Japanese Patent No. 3006303 disclose memory devices in each of which has a self redundancy capability provided in a chip.
In a case where a self-redundancy capability is provided in a chip, however, a memory unit for storing failure information, a defect address generator, an address converter or a register should be provided, beside a BIST circuit, in a chip. This undesirably increases the circuit area of the semiconductor chip. In addition, the interface circuit which is provided between the circuit that achieves the self-redundancy capability and other circuits becomes complicated.
Japanese Unexamined Patent Publication No. 2000-30483 discloses a memory device having a data conversion unit provided outside a chip. When a defective cell is detected in an operational test, the data conversion unit receives address data of the defective cell and generates redundant address data. The memory device performs a redundancy operation in accordance with the redundant address data. The provision of the data conversion unit outside a chip however inevitably increases the cost for the memory device.